A typical semiconductor device in a complementary metal-oxide-semiconductor (CMOS) circuit is formed in a p-well or an n-well in a semiconductor substrate. Since other semiconductor devices are also present in the semiconductor substrate, the semiconductor device requires electrical isolation from adjacent semiconductor devices. Electrical isolation is provided by isolation structures that employ trenches filled with an insulator material. Electrical isolation of one semiconductor device from other devices located in the same well is called “intra-well isolation.” Electrical isolation of the semiconductor device from other devices in an adjacent well of the opposite type is called “inter-well isolation.” In both cases, unintended functionality of parasitic devices, such as parasitic pnp or npn bipolar transistors, formed by various elements of the semiconductor device and adjacent semiconductor devices, needs to be suppressed by placing a dielectric material, typically in the form of a trench isolation structure, in the current paths among the elements of the parasitic devices.
Referring to FIG. 1, a vertical cross-sectional view of a prior art trench isolation structure having minimum separation distances between adjacent device regions is shown which includes an inter-well trench isolation structure 4, and two intra-well trench isolation structures (6, 8). The inter-well isolation structure 4 is located at a boundary between a p-well 11 and an n-well 12, and is bounded by a pair of substantially vertical first trench sidewalls 66 and a substantially horizontal first trench bottom surface 67. One intra-well trench isolation structure 6 is located within the p-well 11, and is bounded by a pair of substantially vertical second trench sidewalls 16 and a substantially horizontal second trench bottom surface 17. The other intra-well trench isolation structure 8 is located within the n-well 12, and is bounded by a pair of substantially vertical third trench sidewalls 18 and a substantially horizontal third trench bottom surface 19. The various isolation structures (4, 6, 8) comprise the same dielectric material.
The depths of the inter-well trench isolation structure 4 and the intra-well trench isolation structures (6, 8) are substantially the same. Variations between the depths of the trench isolation structures (4, 6, 8), that is, variations across the heights of inter-well trench sidewalls 66 and intra-well trench sidewalls (16, 18), are typically caused by process bias between trenches having different widths during a reactive ion etch of the trenches. Therefore, the inter-well trench bottom surface 67 and the intra-well trench bottom surface (17, 19) are substantially at the same depth from a top surface of the semiconductor substrate 8.
Both the p-well 11 and the n-well 12 are located above a substrate layer 10′, which typically has the same doping level as the original semiconductor substrate prior to the doping of the wells (11, 12). Typically, at least one heavily n-doped region 91, such as source and drain regions of an n-type field effect transistor, is located above the p-well 11, and at least one heavily p-doped region 92, such as source and drain regions of a p-type field effect transistor, is located above the n-well 12. The at least one heavily n-doped region 91, the at least one heavily p-doped region 92, the p-well 11, the n-well 12, the two intra-well trench isolation structures (6, 8), the inter-well trench isolation structure 4, and the substrate layer 10′ are located within a semiconductor substrate 8.
An inter-well trench minimum width w1_p of the inter-well trench isolation structure 4 is determined by a combination of the depth of the inter-well trench isolation structure 4 (which is the same as the height of the inter-well trench isolation sidewalls 66), the depths of the at least one heavily n-doped region 91 and the at least on heavily p-doped region 92, the doping levels of the p-well 11 and the n-well 12, the overlay tolerances of lithography processes that are used to form the two wells (11, 12), and the operating voltages of the semiconductor devices abutting the inter-well trench isolation structure 4. An intra-well trench minimum width w2_p of the intra-well trench isolation structures (6, 8) is determined by a combination of the depth of the intra-well trench isolation structure 6, the depth of the at least one heavily n-doped region 91 or the at least one heavily n-doped region 92, the doping level of the p-well 11 or the n-well 12, and the operating voltages of the semiconductor devices abutting the intra-well trench isolation structure 6.
The paths of the weakest inter-well isolation in the prior art isolation structure are represented by a prior art heavily n-doped region to n-well separation distance d2p—p and a prior art heavily p-doped region to p-well separation distance d2n—p in FIG. 1. Likewise, the path of the weakest intra-p-well isolation in the prior art isolation structure is represented by a prior art heavily n-doped region to another heavily n-doped region separation distance d1p—p. The path of the weakest intra-n-well isolation in the prior art isolation structure is represented by a prior art heavily p-doped region to another heavily p-doped region separation distance d1n—p. From geometrical considerations, the inter-well trench minimum width w1_p needs to be greater than the intra-well trench minimum width w2_p due to the presence of the boundary between the p-well 11 and the n-well 12 near the middle of the inter-well trench isolation structure 4.
For example, the depths of the at least one heavily n-doped region 91 and the at least one heavily p-doped region 92 may be about 80 nm, the depths of the various trench isolation structures (4, 6) may be about 280 nm, and the overlay tolerance of lithography processes for ion implantation well definition may be about 30 nm. For 1.1V operation of semiconductor devices, this requires the inter-well trench minimum width w1_p to be about 208 nm such that each of the prior art heavily n-doped region to n-well separation distance d2p—p and the prior art heavily p-doped region to p-well separation distance d2n—p is at least 289 nm. The prior art heavily n-doped region to another heavily n-doped region separation distance d1p—p exceeds twice the difference between the depth of the intra-well trench isolation structure 6 and the depth of the heavily n-doped region 91, and consequently exceeds 400 nm. The intra-well trench minimum width w2_p may be limited not by intra-well device isolation considerations, but by process capability considerations to insure filling of the intra-well trench isolation structures 6 with a trench dielectric material. Considerations on the prior art heavily p-doped region to another heavily p-doped region separation distance d1n—p produces the same result.
Further, the prior art trench isolation structure provides substantially the same depth between the inter-well isolation structure 4 and the intra-well isolation structures (6, 8). Since gap fill characteristics during deposition of dielectric material in a trench depends on the aspect ratio of the trench structure to be filled, a wider trench may have a deeper depth and still be filled. An extended depth would be preferred on an inter-well trench isolation structure having a greater width in this case.
Therefore, there exists a need for an inter-well isolation structure having an increased depth compared to the depth of an intra-well isolation structure having a narrower width and methods of manufacturing the same.
Further, there exists a need for an inter-well trench isolation structure having reduced minimum width compared to the prior art and methods of manufacturing the same.
In addition, there exists a need for such an inter-well trench isolation structure that requires minimal additional processing steps in terms of cost and complexity during the manufacturing.